Semiconductor Dynamic Random Access Memory (DRAM) devices have been applied widely in the integrated circuits with the advance of semiconductor manufacture. Typically, a memory cell consists of a storage capacitor and an access transistor for each bit to be stored by the semiconductor DRAM. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called the bit line and the word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
However, with the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. Namely, the amount of the charge capable of being stored by the capacitor decreases. Besides, for very small memory cells, planar capacitors produced have lower reliability in operation. Accordingly, the important issue currently is how to promote the capacitance and reliability of capacitors with the decreasing scale of the devices and the increasing integration of the integrated circuits.
For resolving the above problems, the manufacture of capacitors tends to increase the surface area of the storage electrode, and results in the development of the various types of capacitors such as the trench capacitor and the stacked capacitor. Except the high dielectric films are used for the capacitor, the bottom electrodes such as the crown shaped structure, the fin shaped structure, the spread shaped structure and cylinder shaped structure are also used to increase the storage efficiency for the capacitors manufactured in the limited areas. However, the capacitances of those stack structures can still hardly to provide enough storage spaces for satisfying the capacitance required for 256M or 1 G DRAM within the limited design rule. Especially, as described above, with the integration of the semiconductor devices increasing, the areas which the various devices occupied become smaller and smaller, and the scales of the devices are sustained shrinking. Thus, the required fin shaped structures and the spread shaped structures can not be defined effectively and successfully in the limited areas by using the conventional technique due to the restriction of the microlithography. Therefore, the yield and storage capacitance of the capacitors manufactured by the prior technique and process can not promoted effectively when the areas that the devices occupied still shrunk.